《FPGA产品设计》(Actel Libero IDE v8.3)Windows/Linux[ISO]
- 资源分类：
- 软件/行业软件
- 发布者：
- 呂翊翀
- 发布时间：
- 2008-04-21 19:11
- 最新更新时间：
- 2008-05-02 08:10
- 浏览次数：
- 加载中..
eMule资源
中文名称：FPGA产品设计
英文名称：Actel Libero IDE v8.3
资源类型：ISO
版本：Windows/Linux
发行时间：2008年
制作发行：Actel
地区：美国
语言：英语
简介：
下载连接来自TLF，未经过安全检测与安装测试，使用者后果自负与本论坛无关
资源版权归作者及其公司所有，如果你喜欢，请购买正版
语言：英语
网址：http://www.actel.com/products/software/libero/
类别：FPGA产品设计
为了扩展其业界领先的专门针对芯片级和系统级节省功率的解决方案，Actel公司宣布推出全新版本Libero集成设计环境(IDE)，具备崭新的重要功能包括功率驱动布局，使设计人员得以进一步优化设计，并可减少典型设计的动态功耗达30%。通过在Libero的SmartPower工具中内置先进的功耗分析功能，这个强化的分析环境将可首次让用户在设计的所有功能模式下深入了解其功率应用。此外，便携产品设计人员更可透过其创新的电池寿命评估功能，以其FPGA设计的功耗曲线为基础，精确计算出电池寿命 — 这是首次在现场可编门阵列(FPGA)设计工具中实现的功能。
Actel软件工程副总裁Jim Davis称：“尽管整个电子行业在提供高功效芯片和系统方面取得了进展，Actel的解决方案无疑为低功耗应用奠下了标准。通过在Libero IDE v8中加入先进的布局优化和功率分析功能，设计人员能够更有效地实现最低功耗的解决方案。”
新版本Libero IDE支持Actel所有的低功耗产品系列，包括超低功耗IGLOO FPGA和混合信号Actel Fusion可编程系统级芯片(PSC)。
功率驱动布局功能降低动态功耗达30%
全新Libero IDE的一个新选项是积极发挥SmartPower中用于功率驱动布局的设计分析数据，使设计人员能够通过减少网络的容性负裁，快速实现动态功耗的节省。IGLOO器件的功耗能平均降低13%，而一些设计更能降低功耗达30%。
电池寿命评估功能为电池供电的便携产品设计人员提供协助
在Libero IDE v8中，SmartPower功能为设计人员提供了创建功率曲线的能力，有助于估算所需的电源和电池要求。功率曲线由用户定义，是FPGA在定制或功能模式组合下的时间百分比，比如活动、待机或Flash*Freeze模式。举例说，为了提供便携或手持设计的电池寿命评估，用户可输入所需的电池电流容量及FPGA的功率曲线，SmartPower便会显示出预计的电池寿命，以及基于目标FPGA的真正功率曲线的实际准确的功耗报告。
增强的SmartPower分析功能实现便携设计的高功效
Libero IDE v8.还增强了SmartPower的功能，能够分析整个FPGA及器件或设计特定部分的功耗，如时域、开关周期，以及假性转换(spurious transition)，而这些因素会个别增加器件的总体功耗。例如，一个精确周期的功率分析选项可让设计人员查看每个时钟周期的峰值功耗，以及整个仿真过程的平均功耗。
SmartPower工具的开关分析选项能够确定引起功耗增加的“危险”，或假性转换状况，让用户找出这些问题并加以修正，从而降低功耗。在典型的设计中，危险状况占据了约20%的功耗。在某些电路中，如组合加法器逻辑，假性转换引起的功耗有可能高达总体功耗的70%。
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______________________________ PROUDLY PRESENTS _______________________________
Actel.Libero.IDE.v8.3.WIndows
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Actel's Flagship FPGA Development Software Libero Integrated Design
Environment (IDE) is Actel's comprehensive software toolset for designing
with all Actel FPGAs. From schematic and/or HDL design, synthesis and
simulation, through floorplanning, place-and-route, timing constraints and
analysis, power analysis, and program file generation, Libero IDE manages
the entire design flow quickly and efficiently.
Libero IDE provides full power optimization and analysis tools for Actel's
low-power flash FPGA families, including IGLOO and ProASIC3L, the latest
addition to the ProASIC3 family. Product Features and Types Libero IDE
offers the latest and best-in-class FPGA development tools from leading
EDA vendors such as Mentor Graphics, SynaptiCAD, and Synplicity. These tools,
combined with Actel developed tools allow you to quickly and easily manage
your Actel FPGA designs. An intuitive user interface and powerful design
manager guides you through the process while organizing design files and
seamlessly managing exchanges between the various tools.
Libero IDE Software Features:
- Powerful project and design flow management
- Full suite of integrated design entry tools and methodologies:
- CoreConsole subsystem creation
- Core Catalog and Configuration
- ViewDraw Schematic Capture
- SmartDesign graphical block subsystem creation with automatic HDL
abstraction
- HDL and HDL templates
- "User-defined blocks" creation flow for design re-use
- Actel macro cells
- Synplify/Synplify Pro AE synthesis fully optimizes Actel FPGA device
performance and area utilization
- Synplify DSP AE performs high-level DSP optimizations within a Simulink
environment
- Test-bench generation including analog stimulus via WaveFormer Lite AE.
Advanced analog stimulus functionality is available from SynaptiCad.
- ModelSim VHDL or Verilog behavioral, post-synthesis and post-layout
simulation capability
- Designer physical design implementation, floorplanning, physical
constraints, and layout
- Timing- and power-driven place-and-route
- SmartTime environment for timing constraint management and analysis
- SmartPower provides comprehensive power analysis
- Interface to FlashPro and Silicon Sculptor programming software
- Identify AE debugging software for Actel flash designs
- Silicon Explorer debugging software for Actel antifuse designs
- Supported on Windows and Linux operating systems
http://www.actel.com/products/software/libero/default.aspx
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1.) unpack the files
2.) burn or mount the image
3.) install
4.) Check Readme.txt into Shooters Dir
If you cant get it - you are not worth it...
### ENJOY ANOTHER FiNE RELEASE BROUGHT TO YOU BY TEAM SHooTERS ###
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3. You are a keygenner and able to handle MD5, RSA, TEA or VB
4. You have a good at Secure Shell/BNC or was Siteop from a good .EU Site
no .de or .us to contact write too SHOOTERS@HUSH.COM
Greetings to : Oddity,Paradox,ENiGMA,ViRiLiTY,TBE all we have forgot !!
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______________________________ PROUDLY PRESENTS _______________________________
Actel.Libero.IDE.v8.3.Linux
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Actel's Flagship FPGA Development Software Libero Integrated Design
Environment (IDE) is Actel's comprehensive software toolset for designing
with all Actel FPGAs. From schematic and/or HDL design, synthesis and
simulation, through floorplanning, place-and-route, timing constraints and
analysis, power analysis, and program file generation, Libero IDE manages
the entire design flow quickly and efficiently.
Libero IDE provides full power optimization and analysis tools for Actel's
low-power flash FPGA families, including IGLOO and ProASIC3L, the latest
addition to the ProASIC3 family. Product Features and Types Libero IDE
offers the latest and best-in-class FPGA development tools from leading
EDA vendors such as Mentor Graphics, SynaptiCAD, and Synplicity. These tools,
combined with Actel developed tools allow you to quickly and easily manage
your Actel FPGA designs. An intuitive user interface and powerful design
manager guides you through the process while organizing design files and
seamlessly managing exchanges between the various tools.
Libero IDE Software Features:
- Powerful project and design flow management
- Full suite of integrated design entry tools and methodologies:
- CoreConsole subsystem creation
- Core Catalog and Configuration
- ViewDraw Schematic Capture
- SmartDesign graphical block subsystem creation with automatic HDL
abstraction
- HDL and HDL templates
- "User-defined blocks" creation flow for design re-use
- Actel macro cells
- Synplify/Synplify Pro AE synthesis fully optimizes Actel FPGA device
performance and area utilization
- Synplify DSP AE performs high-level DSP optimizations within a Simulink
environment
- Test-bench generation including analog stimulus via WaveFormer Lite AE.
Advanced analog stimulus functionality is available from SynaptiCad.
- ModelSim VHDL or Verilog behavioral, post-synthesis and post-layout
simulation capability
- Designer physical design implementation, floorplanning, physical
constraints, and layout
- Timing- and power-driven place-and-route
- SmartTime environment for timing constraint management and analysis
- SmartPower provides comprehensive power analysis
- Interface to FlashPro and Silicon Sculptor programming software
- Identify AE debugging software for Actel flash designs
- Silicon Explorer debugging software for Actel antifuse designs
- Supported on Windows and Linux operating systems
http://www.actel.com/products/software/libero/default.aspx
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1.) unpack the files
2.) burn or mount the image
3.) install
4.) Check Readme.txt into Shooters Dir
If you cant get it - you are not worth it...
### ENJOY ANOTHER FiNE RELEASE BROUGHT TO YOU BY TEAM SHooTERS ###
1. You work at any reseller, distributor or software company and have access
to new unreleased software
2. You are a talented cracker and able to handle: Dongle, FlexLM, Armadillo,
Asprotect, HASP oR Wibu
3. You are a keygenner and able to handle MD5, RSA, TEA or VB
4. You have a good at Secure Shell/BNC or was Siteop from a good .EU Site
no .de or .us to contact write too SHOOTERS@HUSH.COM
Greetings to : Oddity,Paradox,ENiGMA,ViRiLiTY,TBE all we have forgot !!
▄▄█████████▄
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▓▒░░░░░░░░░░░ SHOOTERS@HUSH.COM █▀▀▀▀▀▀▀▀▀▀ █████████████████████▌▀ ▄▄███▄ ▀▀█
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FLY OUT 2 ALL OUTLAWS OUT THERE █ ▐███████████████████████████████▀▀▀▄▀ ░░░ █
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▀▀▀▀▀▀▀▀▀ ▀▀▀ ▀ ▀ ▀▀▀▀▀▀▀▀▀▀ █ ░░░░░░░░░░░░░░ ▀▄░▒ ▄----▄▀░░▀█ ░░░░░░░░░ █
(",) █ ░░░░░░░░░░░░░░░░ ░▒ ████░ ▓░░▄ ░░░░░░░░░░ █
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▓▒░ "siR -- where are you?" ░▒▓ █▄▄▄▄▄▄▄▄▄▄▄▄▄▄▄▄▄ █ █▓▒▒▒░ █░ ▄▀▄▄▄▄▄▄▄▄▄▄▄█
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░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░
░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░░░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░░░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░░░
░ ░░░ ░ ░ ░ ░ ░ ░ ░ ░░░ ░ ░░░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░ ░░░ ░ ░░░ ░ ░ ░ ░ ░ ░ ░ EOF
[/CODEBOX]
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